Behavioral Simulation of Decision Feedback Equalizer Architectures Using CppSim
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چکیده
Setup Introduction A. Challenges in High Speed Serial Link Design B. Signal Restoration using a Decision Feedback Equalizer (DFE) Preliminaries A. Opening Sue2 Schematics B. Running CppSim Simulations Plotting Time-Domain Results A. Output signal plots B. Output signal Eye Diagrams C. RMS Jitter Examining Non-Idealities A. Intersymbol Interference (ISI) B. Reflections C. Non-Linearity and Offset D. Gain-Bandwidth Limitations, Clock-to-Q Delays, and Metastability DFE Calibration DFE Architectures A. Prototypical DFE B. Half-Rate DFE with One-Tap of Speculation I. Simulating and Analyzing Speculative Half-Rate Architecture in CppSim Conclusion Appendix: Generating Channel Impulse Response from Measured Data
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